View ISPGAL22V10_3653207.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

publication# 16559 rev. c amendment /0 issue date: february 1996 2-197 advanced micro devices pal22v10 family, ampal22v10/a 24-pin ttl versatile pal device final com'l: -7/10/15 distinctive characteristics n as fast as 7.5-ns propagation delay and 91 mhz f max (external) n 10 macrocells programmable as registered or combinatorial, and active high or active low to match application needs n varied product term distribution allows up to 16 product terms per output for complex functions n global asynchronous reset and synchronous preset for initialization n power-up reset for initialization and register preload for testability n extensive third-party software and programmer support through fusionpld partners n 24-pin skinnydip, 24-pin flatpack and 28-pin plcc and lcc packages save space general description the pal22v10 provides user-programmable logic for replacing conventional ssi/msi gates and flip-flops at a reduced chip count. the pal22v10 device implements the familiar boolean logic transfer function, the sum of products. the pal de- vice is a programmable and array driving a fixed or array. the and array is programmed to create custom product terms, while the or array sums selected terms at the outputs. the product terms are connected to the fixed or array with a varied distribution from 8 to 16 across the outputs (see block diagram). the or sum of the products feeds the output macrocell. each macrocell can be pro- grammed as registered or combinatorial, and active high or active low. the output configuration is determined by two fuses controlling two multiplexers in each macrocell. amds fusionpld program allows pal22v10 designs to be implemented using a wide variety of popular indus- try-standard design tools. by working closely with the fusionpld partners, amd certifies that the tools pro- vide accurate, quality support. by ensuring that third- party tools are available, costs are lowered because a designer does not have to buy a complete set of new tools for each device. the fusionpld program also greatly reduces design time since a designer can use a tool that is already installed and familiar. block diagram output logic macro cell output logic macro cell output logic macro cell output logic macro cell output logic macro cell output logic macro cell output logic macro cell output logic macro cell output logic macro cell output logic macro cell reset preset programmable and array (44 x 132) clk/i 0 1 i 1 - i 11 11 81012141616141210 8 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 16559c-1
amd 2-198 pal22v10 family connection diagrams top view v cc skinnydip/flatpack 16559c-2 pin designations clk = clock gnd = ground i = input i/o = input/output nc = no connect v cc = supply voltage note: pin 1 is marked for orientation. plcc/lcc i 1 i 3 i 5 i 7 i 9 gnd i/o 9 i/o 7 i/o 5 i/o 3 i/o 1 i 11 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 i/o 8 i/o 6 i/o 4 i/o 2 i/o 0 clk/i 0 i 2 i 4 i 6 i 8 i 10 1 32 4 5 6 7 8 9 10 11 25 24 23 22 21 20 19 28 27 26 15 13 14 12 16 17 18 i 3 i 4 i 5 nc i 6 i 7 i 8 i/o 7 i/o 6 nc i/o 4 i/o 3 i 2 i 1 clk/i 0 nc v cc nc i 9 i 10 i/o 1 i/o 9 i/o 8 i/o 5 i/o 2 i 11 i/o 0 gnd 16559c-3
amd 2-199 pal22v10-7/10/15, ampal22v10a (com'l) ordering information commercial products number of array inputs output type v = versatile speed -7 = 7.5 ns t pd -10 = 10 ns t pd -15 = 15 ns t pd a = 25 ns t pd package type p = 24-pin 300 mil plastic skinnydip (pd3024) j = 28-pin plastic leaded chip carrier (pl 028) family type pal or ampal = programmable array logic amd programmable logic products for commercial applications are available with several ordering options. the order number (valid combination) is formed by a combination of: pal22v10-10 pc, jc valid combinations valid combinations valid combinations lists configurations planned to be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. pal 22 v 10 -7 p c number of outputs operating conditions c = commercial (0 c to +75 c) optional processing blank = standard processing pal22v10-7 pal22v10-15 ampal22v10a
amd 2-200 pal22v10 family functional description the pal22v10 allows the systems engineer to imple- ment a design on-chip, by opening fuse links to config- ure and and or gates within the device, according to the desired logic function. complex interconnections between gates, which previously required time- consuming layout, are lifted from the pc board and placed on silicon, where they can be easily modified dur- ing prototyping or production. product terms with all fuses opened assume the logical high state; product terms connected to both true and complement of any single input assume the logical low state. the pal22v10 has 12 inputs and 10 i/o macrocells. the macrocell (figure 1) allows one of four potential out- put configurations; registered output or combinatorial i/o, active high or active low (see figure 2). the configu- ration choice is made according to the users design specification and corresponding programming of the configuration bits s 0 C s 1 . multiplexer controls initially are connected to ground (0) through a programmable fuse, selecting the 0 path through the multiplexer. pro- gramming the fuse disconnects the control line from gnd and it is driven to a high level, selecting the 1 path. the device is produced with a fuse link at each input to the and gate array, and connections may be selectively removed by applying appropriate voltages to the circuit. variable input/output pin ratio the pal22v10 has twelve dedicated input lines, and each macrocell output can be an i/o pin. buffers for de- vice inputs have complementary outputs to provide user-programmable input signal polarity. unused input pins should be tied to v cc or gnd. clk s 1 10 11 00 01 ar sp 0 1 i/o n s 0 s 1 s 0 output configuration 0 0 registered/active low 0 1 registered/active high 1 0 combinatorial/active low 1 1 combinatorial/active high 0 = unprogrammed fuse 1 = programmed fuse 16559c-4 dq q figure 1. output logic macrocell diagram
amd 2-201 pal22v10 family registered output configuration each macrocell of the pal22v10 includes a d-type flip- flop for data storage and synchronization. the flip-flop is loaded on the low-to-high transition of the clock in- put. in the registered configuration (s 1 = 0), the array feedback is from q of the flip-flop. combinatorial i/o configuration any macrocell can be configured as combinatorial by selecting the multiplexer path that bypasses the flip-flop (s 1 = 1). in the combinatorial configuration the feedback is from the pin. dq q clk sp ar registered/active low s 0 = 0 s 1 = 0 combinatorial/active low s 0 = 0 s 1 = 1 dq q clk sp ar registered/active high s 0 = 1 s 1 = 0 combinatorial/active high s 0 = 1 s 1 = 1 16559c-5 figure 2. macrocell configuration options programmable three-state outputs each output has a three-state output buffer with three- state control. a product term controls the buffer, allow- ing enable and disable to be a function of any product of device inputs or output feedback. the combinatorial output provides a bidirectional i/o pin, and may be con- figured as a dedicated input if the buffer is always dis- abled. programmable output polarity the polarity of each macrocell output can be active high or active low, either to match output signal needs or to reduce product terms. programmable polarity allows boolean expressions to be written in their most compact form (true or inverted), and the output can still be of the desired polarity. it can also save demorganizing efforts. selection is controlled by programmable bit s 0 in the output macrocell, and affects both registered and com- binatorial outputs. selection is automatic, based on the design specification and pin definitions. preset/reset for initialization, the pal22v10 has preset and reset product terms. these terms are connected to all regis- tered outputs. when the synchronous preset (sp) product term is asserted high, the output registers will be loaded with a high on the next low-to-high clock transition. when the asynchronous reset (ar) product term is asserted high, the output registers will be imme- diately loaded with a low independent of the clock. note that preset and reset control the flip-flop, not the output pin. the output level is determined by the output polarity selected. power-up reset all flip-flops power-up to a logic low for predictable system initialization. outputs of the pal22v10 will de- pend on the programmed output polarity. the v cc rise must be monotonic and the reset delay time is 1000 ns maximum.
amd 2-202 pal22v10 family register preload the register on the pal22v10 can be preloaded from the output pins to facilitate functional testing of complex state machine designs. this feature allows direct load- ing of arbitrary states, making it unnecessary to cycle through long test vector sequences to reach a desired state. in addition, transitions from illegal states can be verified by loading illegal states and observing proper recovery. security fuse after programming and verification, a pal22v10 design can be secured by programming the security fuse. once programmed, this fuse defeats readback of the internal programmed pattern by a device programmer, securing proprietary designs from competitors. when the secu- rity fuse is programmed, the array will read as if every fuse is programmed, and preload will be disabled. programming the pal22v10 can be programmed on standard logic programmers. approved programmers are listed at the end of this data book. quality and testability the pal22v10 offers a very high level of built-in quality. extra programmable fuses, test words and test columns provide a means of verifying performance of all ac and dc parameters. in addition, this verifies complete programmability and functionality of the device to pro- vide the highest programming yields and post-program- ming functional yields in the industry. technology the ampal22v10a is fabricated with amds diffusion- isolated bipolar process. the array connections are formed with highly reliable ptsi fuse. the pal22v10-15, -10 and -7 are fabricated with amds diffusion-isolated bipolar process. this process reduces parasitic capacitances and minimum geome- tries to provide higher performance. the array connections are formed with ptsi fuses on the -15, and tiw fuses on the -7 and -10 for reliable operation.
amd 2-203 pal22v10 family logic diagram skinnydip (plcc/lcc) pinouts 16559c-6 0 1 9 sp ar 0 34 78 11121516 19202324 2728313235363940 43 10 20 21 0 34 78 11121516192023242728313235363940 43 clk/i 0 1 (2) 2 (3) i 1 3 (4) i 2 4 (5) i 3 5 (6) i 4 6 (7) i 5 7 (9) i 6 8 (10) i 7 9 (11) i 8 10 (12) i 9 11 (13) i 10 12 (14) gnd 24 (28) v cc (16) i 13 11 34 33 48 49 65 66 82 83 97 98 110 111 121 122 130 131 i/o 9 23 (27) 8 i/o 22 (26) i/o 21 (25) 7 i/o 20 (24) 6 5 i/o 19 (23) 4 i/o 18 (21) i/o 17 (20) 3 i/o 16 (19) 2 i/o 15 (18) 1 i/o 14 (17) 0 d sp ar q q 0 1 10 1 1 00 0 1 d sp ar q q 0 1 10 1 1 00 0 1 d sp ar q q 0 1 10 1 1 00 0 1 d sp ar q q 0 1 10 1 1 00 0 1 d sp ar q q 0 1 10 1 1 00 0 1 d sp ar q q 0 1 10 1 1 00 0 1 d sp ar q q 0 1 10 1 1 00 0 1 d sp ar q 0 1 10 1 1 00 0 1 d sp ar q 0 1 10 1 1 00 0 1 d sp ar q 0 1 10 1 1 00 0 1 q q q
amd 2-204 pal22v10-7 (com'l) absolute maximum ratings storage temperature C65 c to +150 c . . . . . . . . . . . ambient temperature with power applied C55 c to +125 c . . . . . . . . . . . . . . . . . supply voltage with respect to ground C0.5 v to +7.0 v . . . . . . . . . . . . . dc input voltage C1.2 v to v cc + 0.5 v . . . . . . . . . . . dc output or i/o pin voltage C0.5 v to v cc + 0.5 v . stresses above those listed under absolute maximum rat- ings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maxi- mum ratings for extended periods may affect device reliabil- ity. programming conditions may differ. operating ranges commercial (c) devices ambient temperature (t a ) operating in free air 0 c to +75 c . . . . . . . . . . . . . . supply voltage (v cc ) with respect to ground +4.75 v to +5.25 v . . . . . . . . operating ranges define those limits between which the func- tionality of the device is guaranteed. dc characteristics over commercial operating ranges unless otherwise specified parameter symbol parameter description test conditions min max unit v oh output high voltage i oh = C3.2 ma v in = v ih or v il 2.4 v v cc = min v ol output low voltage i ol = 16 ma v in = v ih or v il 0.5 v v cc = min v ih input high voltage guaranteed input logical high 2.0 v voltage for all inputs (note 1) v il input low voltage guaranteed input logical low 0.8 v voltage for all inputs (note 1) v i input clamp voltage i in = C18 ma, v cc = min C1.2 v i ih input high current v in = 2.7 v, v cc = max (note 2) 25 m a i il input low current v in = 0.4 v, v cc = max C100 (note 2) C150 i i maximum input current v in = 5.5 v, v cc = max 1 ma i ozh off-state output leakage v out = 2.7 v, v cc = max 100 m a current high v in = v ih or v il (note 2) i ozl off-state output leakage v out = 0.4 v, v cc = max C100 m a current low v in = v ih or v il (note 2) i sc output short-circuit current v out = 0.5 v, v cc = max (note 3) C30 C130 ma i cc supply current v in = 0 v, outputs open (i out = 0 ma) 220 ma v cc = max notes: 1. these are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 3. not more than one output should be tested at a time. duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation. clk m a input
amd 2-205 pal22v10-7 (com'l) capacitance (note 1) parameter symbol parameter description test conditions typ unit c in input capacitance v in = 2.0 v 6 c out output capacitance v out = 2.0 v 5 note: 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. v cc = 5.0 v t a = 25 c f = 1 mhz pf switching characteristics over commercial operating ranges (note 2) parameter min symbol parameter description (note 3) max unit t pd input or feedback to combinatorial output 1 7.5 ns t s setup time from input, feedback or sp to clock 5 ns t h hold time 0 ns t co clock to output 1 6 ns t skewr skew between registered outputs (note 5) 1 ns t ar asynchronous reset to registered output 12 ns t arw asynchronous reset width 8 ns t arr asynchronous reset recovery time 8 ns t spr synchronous preset recovery time 5 ns t wl low 4 ns t wh high 4 ns external feedback 1/(t s + t co ) 91 mhz f max internal feedback (f cnt ) 1/(t s + t cf ) (note 6) 100 mhz no feedback 1/(t wh + t wl ) 125 mhz t ea input to output enable using product term control 8 ns t er input to output disable using product term control 7.5 ns clock width maximum frequency (note 4) notes: 2. see switching test circuit for test conditions. 3. output delay minimums are measured under best-case conditions. 4. these parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 5. skew is measured with all outputs switching in the same direction. 6. t cf is a calculated value and is not guaranteed. t cf can be found using the following equation: t cf = 1/f max (internal feedback) C t s .
amd 2-206 pal22v10-10 (com'l) absolute maximum ratings storage temperature C65 c to +150 c . . . . . . . . . . . ambient temperature with power applied C55 c to +125 c . . . . . . . . . . . . . . . . . supply voltage with respect to ground C0.5 v to +7.0 v . . . . . . . . . . . . . dc input voltage C1.2 v to v cc + 0.5 v . . . . . . . . . . . dc output or i/o pin voltage C0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . stresses above those listed under absolute maximum rat- ings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maxi- mum ratings for extended periods may affect device reliabil- ity. programming conditions may differ. operating ranges commercial (c) devices ambient temperature (t a ) operating in free air 0 c to +75 c . . . . . . . . . . . . . . supply voltage (v cc ) with respect to ground +4.75 v to +5.25 v . . . . . . . . operating ranges define those limits between which the func- tionality of the device is guaranteed. dc characteristics over commercial operating ranges unless otherwise specified parameter symbol parameter description test conditions min max unit v oh output high voltage i oh = C3.2 ma v in = v ih or v il 2.4 v v cc = min v ol output low voltage i ol = 16 ma v in = v ih or v il 0.5 v v cc = min v ih input high voltage guaranteed input logical high 2.0 v voltage for all inputs (note 1) v il input low voltage guaranteed input logical low 0.8 v voltage for all inputs (note 1) v i input clamp voltage i in = C18 ma, v cc = min C1.2 v i ih input high current v in = 2.7 v, v cc = max (note 2) 25 m a i il input low current v in = 0.4 v, v cc = max C100 (note 2) C150 i i maximum input current v in = 5.5 v, v cc = max 1 ma i ozh off-state output leakage v out = 2.7 v, v cc = max 100 m a current high v in = v ih or v il (note 2) i ozl off-state output leakage v out = 0.4 v, v cc = max C100 m a current low v in = v ih or v il (note 2) i sc output short-circuit current v out = 0.5 v, v cc = max (note 3) C30 C130 ma i cc supply current v in = 0 v, outputs open (i out = 0 ma) 180 ma v cc = max notes: 1. these are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 3. not more than one output should be tested at a time. duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation. m a clk input
amd 2-207 pal22v10-10 (com'l) capacitance (note 1) parameter symbol parameter description test conditions typ unit c in input capacitance v in = 2.0 v 6 c out output capacitance v out = 2.0 v 5 note: 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. v cc = 5.0 v t a = 25 c f = 1 mhz pf switching characteristics over commercial operating ranges (note 2) parameter min symbol parameter description (note 3) max unit t pd input or feedback to combinatorial output 1 10 ns t s setup time from input, feedback or sp to clock 7 ns t h hold time 0 ns t co clock to output 1 7 ns t ar asynchronous reset to registered output 15 ns t arw asynchronous reset width 10 ns t arr asynchronous reset recovery time 8 ns t spr synchronous preset recovery time 8 ns t wl low 5 ns t wh high 5 ns external feedback 1/(t s + t co ) 71 mhz f max internal feedback (f cnt ) 1/(t s + t cf ) (note 5) 80 mhz no feedback 1/(t wh + t wl ) 100 mhz t ea input to output enable using product term control 11 ns t er input to output disable using product term control 9 ns clock width maximum frequency (note 4) notes: 2. see switching test circuit for test conditions. 3. output delay minimums are measured under best-case conditions. 4. these parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 5. t cf is a calculated value and is not guaranteed. t cf can be found using the following equation: t cf = 1/f max (internal feedback) C t s .
amd 2-208 pal22v10-15 (com'l) absolute maximum ratings storage temperature C65 c to +150 c . . . . . . . . . . . ambient temperature with power applied C55 c to +125 c . . . . . . . . . . . . . . . . . supply voltage with respect to ground C0.5 v to +7.0 v . . . . . . . . . . . . . dc input voltage C0.5 v to v cc + 0.5 v . . . . . . . . . . . dc input current C30 ma to +5 ma . . . . . . . . . . . . . dc output or i/o pin voltage C0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . static discharge voltage 2001 v . . . . . . . . . . . . . . . . . stresses above those listed under absolute maximum rat- ings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maxi- mum ratings for extended periods may affect device reliabil- ity. programming conditions may differ. operating ranges commercial (c) devices ambient temperature (t a ) operating in free air 0 c to +75 c . . . . . . . . . . . . . . supply voltage (v cc ) with respect to ground +4.75 v to +5.25 v . . . . . . . . operating ranges define those limits between which the func- tionality of the device is guaranteed. dc characteristics over commercial operating ranges unless otherwise specified notes: 1. these are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 3. not more than one output should be tested at a time. duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation. parameter symbol parameter description test conditions min max unit v oh output high voltage i oh = C3.2 ma v in = v ih or v il 2.4 v v cc = min v ol output low voltage i ol = 16 ma v in = v ih or v il 0.5 v v cc = min v ih input high voltage guaranteed input logical high 2.0 v voltage for all inputs (note 1) v il input low voltage guaranteed input logical low 0.8 v voltage for all inputs (note 1) v i input clamp voltage i in = C18 ma, v cc = min C1.2 v i ih input high current v in = 2.7 v, v cc = max (note 2) 25 m a i il input low current v in = 0.4 v, v cc = max (note 2) C100 m a i i maximum input current v in = 5.5 v, v cc = max 1 ma i ozh off-state output leakage v out = 2.7 v, v cc = max 100 m a current high v in = v ih or v il (note 2) i ozl off-state output leakage v out = 0.4 v, v cc = max C100 m a current low v in = v ih or v il (note 2) i sc output short-circuit current v out = 0.5 v, v cc = max (note 3) C30 C130 ma i cc supply current v in = 0 v, outputs open (i out = 0 ma) 180 ma v cc = max
amd 2-209 pal22v10-15 (com'l) capacitance (note 1) 9 parameter symbol parameter description test conditions typ unit c in input capacitance v in = 2.0 v c out output capacitance v out = 2.0 v 5 note: 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. v cc = 5.0 v t a = 25 c f = 1 mhz pf 6 switching characteristics over commercial operating ranges (note 2) parameter min symbol parameter description (note 3) max unit t pd input or feedback to combinatorial output 15 ns t s setup time from input, feedback or sp to clock 10 ns t h hold time 0 ns t co clock to output 10 ns t ar asynchronous reset to registered output 20 ns t arw asynchronous reset width 15 ns t arr asynchronous reset recovery time 10 ns t spr synchronous preset recovery time 10 ns t wl low 6 ns t wh high 6 ns external feedback 1/(t s + t co ) 50 mhz f max internal feedback (f cnt ) 1/(t s + t cf ) (note 5) 80 mhz no feedback 1/(t wh + t wl ) 83 mhz t ea input to output enable using product term control 15 ns t er input to output disable using product term control 15 ns clock width maximum frequency (note 4) notes: 2. see switching test circuit for test conditions. 3. output delay minimums are measured under best-case conditions. 4. these parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 5. t cf is a calculated value and is not guaranteed. t cf can be found using the following equation: t cf = 1/f max (internal feedback) C t s .
amd 2-210 ampal22v10a (com'l) absolute maximum ratings storage temperature C65 c to +150 c . . . . . . . . . . . ambient temperature with power applied C55 c to +125 c . . . . . . . . . . . . . . . . . supply voltage with respect to ground C0.5 v to +7.0 v . . . . . . . . . . . . . dc input voltage C0.5 v to +5.5 v . . . . . . . . . . . . . . . dc input current C30 ma to +5 ma . . . . . . . . . . . . . . dc output or i/o pin voltage C0.5 v to v cc max . . . stresses above those listed under absolute maximum rat- ings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maxi- mum ratings for extended periods may affect device reliabil- ity. programming conditions may differ. operating ranges commercial (c) devices ambient temperature (t a ) operating in free air 0 c to +75 c . . . . . . . . . . . . . . supply voltage (v cc ) with respect to ground +4.75 v to +5.25 v . . . . . . . . operating ranges define those limits between which the func- tionality of the device is guaranteed. dc characteristics over commercial operating ranges unless otherwise specified notes: 1. these are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 3. not more than one output should be tested at a time. duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation. parameter symbol parameter description test conditions min max unit v oh output high voltage i oh = C3.2 ma v in = v ih or v il 2.4 v v cc = min v ol output low voltage i ol = 16 ma v in = v ih or v il 0.5 v v cc = min v ih input high voltage guaranteed input logical high 2.0 v voltage for all inputs (note 1) v il input low voltage guaranteed input logical low 0.8 v voltage for all inputs (note 1) v i input clamp voltage i in = C18 ma, v cc = min C1.2 v i ih input high current v in = 2.7 v, v cc = max (note 2) 25 m a i il input low current v in = 0.4 v, v cc = max (note 2) C100 m a i i maximum input current v in = 5.5 v, v cc = max 1 ma i ozh off-state output leakage v out = 2.7 v, v cc = max 100 m a current high v in = v ih or v il (note 2) i ozl off-state output leakage v out = 0.4 v, v cc = max C100 m a current low v in = v ih or v il (note 2) i sc output short-circuit current v out = 0.5 v, v cc = max (note 3) C30 C90 ma i cc supply current v in = 0 v, outputs open (i out = 0 ma) 180 ma v cc = max
amd 2-211 ampal22v10a (com'l) capacitance (note 1) parameter symbol parameter description test conditions typ unit c in input capacitance v in = 2.0 v c out output capacitance v out = 2.0 v 9 note: 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. v cc = 5.0 v t a = 25 c f = 1 mhz pf 11 6 switching characteristics over commercial operating ranges (note 2) parameter symbol parameter description min max unit t pd input or feedback to combinatorial output 25 ns t s setup time from input, feedback or sp to clock 20 ns t h hold time 0 ns t co clock to output 15 ns t ar asynchronous reset to registered output 30 ns t arw asynchronous reset width 25 ns t arr asynchronous reset recovery time 35 ns t spr synchronous preset recovery time 20 ns t wl low 15 ns t wh high 15 ns f max external feedback 1/(t s + t co ) 28.5 mhz t ea input to output enable using product term control 25 ns t er input to output disable using product term control 25 ns clock width maximum frequency (note 3) notes: 2. see switching test circuit for test conditions. 3. these parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected.
amd 2-212 pal22v10 family switching waveforms notes: 1. v t = 1.5 v. 2. input pulse amplitude 0 v to 3.0 v. 3. input rise and fall times 2 ns C 4 ns typical. t pd input or feedback combinatorial output v t v t 16559c-7 combinatorial output v t input or feedback registered output registered output 16559c-8 t s t co v t t h v t clock t wh clock clock width v t t wl 16559c-9 v t v t input or feedback output input to output disable/enable 16559c-10 t er t ea v oh - 0.5v v ol + 0.5v v t v t t arr t arw v t t ar asynchronous reset 16559c-11 clock registered output input asserting asynchronous reset v t v t t spr v t t s synchronous preset 16559c-12 clock registered output input asserting synchronous preset t h t co
amd 2-213 pal22v10 family key to switching waveforms 16559c-13 c l output r 1 r 2 s 1 test point 5 v switching test circuit ks000010-pal must be steady may change from h to l may change from l to h does not apply dont care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance off state waveform inputs outputs commercial measured specification s 1 c l r 1 r 2 output value t pd , t co closed all except -7: 1.5 v t ea z ? h: open 50 pf 300 w 390 w 1.5 v z ? l: closed t er h ? z: open 5 pf -7: h ? z: v oh C 0.5 v l ? z: closed 300 w l ? z: v ol + 0.5 v
amd 2-214 pal22v10-10 measured switching characteristics for the pal22v10-10 v cc = 4.75 v, t a = 75 c (note 1) 10 9 8 7 1 2 34 5 6 78 number of outputs switching 16559c-14 t pd vs. number of outputs switching 13 11 9 7 0 40 80 120 c l , pf t pd , ns t pd , ns 160 200 t pd vs. load capacitance 16559c-15 910 12 10 8 note : 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where t pd may be affected.
amd 2-215 pal22v10 family input/output equivalent schematics 16559c-16 typical input input program/verify circuitry v cc 16559c-17 output 40 w nom typical output input, i/o pins preload circuitry program/verify/ test circuitry v cc
amd 2-216 pal22v10 family power-up reset the power-up reset feature ensures that all flip-flops will be reset to low after the device has been powered up. the output state will depend on the programmed pat- tern. this feature is valuable in simplifying state ma- chine initialization. a timing diagram and parameter ta- ble are shown below. due to the synchronous operation of the power-up reset and the wide range of ways v cc can rise to its steady state, two conditions are required to ensure a valid power-up reset. these conditions are: n the v cc rise must be monotonic. n following reset, the clock input must not be driven from low to high until all applicable input and feed- back setup times are met. parameter symbol parameter description max unit t pr power-up reset time 1000 ns t s input or feedback setup time t wl clock width low 16559c-18 t pr t wl t s 4 v v cc power registered active-low output clock see switching characteristics power-up reset waveform

▲Up To Search▲

Price & Availability of ISPGAL22V10

	To Download ISPGAL22V10 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .